1. Technical Field
The invention relates to circuit design. More particularly, the invention relates to race condition detection and expression.
2. Description of the Prior Art
A race condition is a very common and serious issue in circuit design. An example of a race condition is shown in Table 1 below by a Verilog program.
TABLE 1Race Conditionmodule t(clk, a, b, c);input clk;output a;input  b;input  c;reg   a;always @(posedge clk) a = b;always @(posedge clk) a = c;endmodule
In this example, when the clock “clk” changes from “0” to “1”, that is at the positive edge of clk, either a=b may happen first or a=c may happen first. That is, they may race each other. As a result, signal “a” may get the value of “b” or “c.” In circuit design, this is an undesired effect because the final value of “a” is nondeterministic.
A race condition is defined as a situation where reading a variable may result in one of several values nondeterministically. To avoid races, circuits are usually designed in some specific ways to prevent a race condition.
Another approach is to detect during the design stage if the circuits may have races. Some circuit simulation tools can detect a race condition when the simulator finds that, during the same simulation cycle, a signal (also referred to as a wire, register, or variable) is being written to two or more times, or being written to as well as being read from. See, for example, U.S. Pat. Nos. 5,383,167; 5,818,263; 5,901,061; and 6,009,256.)
An example of a simulator which can detect race conditions is the VCS Verilog Simulator from Synopsys. Such simulators need test vectors to conduct the simulation. The race may or may not be detected depending the way in which the test vectors exercise the design.
It would be advantageous to provide a method and apparatus for improved race detection and expression.